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1200 MHz to 2500 MHz Balanced Mixer, LO Buffer and RF Balun ADL5365
FEATURES
RF frequency range of 1200 MHz to 2500 MHz IF frequency range of dc to 450 MHz Power conversion loss: 7.3 dB SSB noise figure of 8.3 dB SSB noise figure with 5 dBm blocker of 18.5 dB Input IP3 of 36 dBm Typical LO drive of 0 dBm Single-ended, 50 RF and LO input ports High isolation SPDT LO input switch Single-supply operation: 3.3 V to 5 V Exposed paddle 5 mm x 5 mm, 20-lead LFCSP 1500 V HBM/500 V FICDM ESD performance
FUNCTIONAL BLOCK DIAGRAM
VCMI
20
IFOP
19
IFON
18
PWDN
17
COMM
16
ADL5365
VPMX 1
15
LOI2
RFIN 2
14
VPSW
RFCT 3 BIAS GENERATOR COMM 4
13
VGS1
12
VGS0
APPLICATIONS
Cellular base station receivers Transmit observation receivers Radio link downconverters
COMM 5
6 7 8 9 10
08082-001
11
LOI1
VLO3 NC = NO CONNECT
LGM3
VLO2
LOSW
NC
GENERAL DESCRIPTION
The ADL5365 uses a highly linear, doubly balanced passive mixer core along with integrated RF and LO balancing circuitry to allow for single-ended operation. The ADL5365 incorporates an RF balun, allowing for optimal performance over a 1200 MHz to 2500 MHz RF input frequency range using high-side LO injection for RF frequencies from 1700 MHz to 2500 MHz and low-side injection for frequencies from 1200 MHz to 1700 MHz. The balanced passive mixer arrangement provides good LO-toRF leakage, typically better than -30 dBm, and excellent intermodulation performance. The balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in the degradation of dynamic performance.
Figure 1.
The ADL5365 provides two switched LO paths that can be used in TDD applications where it is desirable to rapidly switch between two local oscillators. LO current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. For low voltage applications, the ADL5365 is capable of operation at voltages down to 3.3 V with substantially reduced current. Under low voltage operation, an additional logic pin is provided to power down (<200 A) the circuit when desired. The ADL5365 is fabricated using a BiCMOS high performance IC process. The device is available in a 5 mm x 5 mm, 20-lead LFCSP and operates over a -40C to +85C temperature range. An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency (MHz) 500 to 1700 1200 to 2500 Single Mixer ADL5367 ADL5365 Single Mixer + IF Amp ADL5357 ADL5355 Dual Mixer + IF Amp ADL5358 ADL5356
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
ADL5365 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 5 V Performance ........................................................................... 4 3.3 V Performance ........................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 5 V Performance ........................................................................... 7 3.3 V Performance ...................................................................... 14 Upconversion .............................................................................. 15 Spurious Performance ............................................................... 16 Circuit Description......................................................................... 17 RF Subsystem .............................................................................. 17 LO Subsystem ............................................................................. 17 Applications Information .............................................................. 19 Basic Connections ...................................................................... 19 IF Port .......................................................................................... 19 Bias Resistor Selection ............................................................... 19 Mixer VGS Control DAC .......................................................... 19 Evaluation Board ............................................................................ 20 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
10/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5365 SPECIFICATIONS
VS = 5 V, IS = 95 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, ZO = 50 , unless otherwise noted. Table 2.
Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage 1 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range POWER-DOWN (PWDN) INTERFACE 2 PWDN Threshold Logic 0 Level Logic 1 Level PWDN Response Time PWDN Input Bias Current Test Conditions/Comments Tunable to >20 dB over a limited bandwidth 1500 Differential impedance, f = 200 MHz Externally generated dc 3.3 -6 36||2 5.0 0 17 50 450 5.5 +10 Min Typ 16 50 2700 Max Unit dB MHz ||pF MHz V dBm dB MHz V V V ns ns A A
1230 1.0
2470
0.4 1.4 Device enabled, IF output to 90% of its final level Device disabled, supply current < 5 mA Device enabled Device disabled 160 220 0.0 70
1 2
Apply the supply voltage from the external circuit through the choke inductors. PWDN function is intended for use with VS 3.6 V only.
Rev. 0 | Page 3 of 24
ADL5365
5 V PERFORMANCE
VS = 5 V, IS = 95 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted. Table 3.
Parameter DYNAMIC PERFORMANCE Power Conversion Loss Voltage Conversion Loss SSB Noise Figure SSB Noise Figure Under Blocking Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) 1 LO-to-IF Leakage LO-to-RF Leakage RF-to-IF Isolation IF/2 Spurious IF/3 Spurious POWER SUPPLY Positive Supply Voltage Quiescent Current
1
Test Conditions\Comments Including 1:1 IF port transformer and PCB loss ZSOURCE = 50 , differential ZLOAD = 50 differential 5 dBm blocker present 10 MHz from wanted RF input, LO source filtered fRF1 = 1899.5 MHz, fRF2 = 1900.5 MHz, fLO = 1697MHz, each RF tone at 0 dBm fRF1 = 1950 MHz, fRF2 = 1900 MHz, fLO = 1697 MHz, each RF tone at 0 dBm Exceeding 20 dBm RF power results in damage to the device Unfiltered IF output
Min 6.5
Typ 7.3 8.3 18.5
Max 8.4
Unit dB dB dB dB dBm dBm dBm dBm dBm dBc dBc dBc
27
36 67 25 -18 -33 -50 -65 -71
0 dBm input power 0 dBm input power 4.5 Resistor programmable
5 95
5.5
V mA
Exceeding 20 dBm RF power results in damage to the device.
3.3 V PERFORMANCE
VS = 3.3 V, IS = 56 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, R9 = 226 , VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted. Table 4.
Parameter DYNAMIC PERFORMANCE Power Conversion Loss Voltage Conversion Loss SSB Noise Figure Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) POWER INTERFACE Supply Voltage Quiescent Current Power-Down Current Test Conditions/Comments Including 1:1 IF port transformer and PCB loss ZSOURCE = 50 , differential ZLOAD = 50 differential fRF1 = 1899.5 MHz, fRF2 = 1900.5 MHz, fLO = 1697 MHz, each RF tone at 0 dBm fRF1 = 1950 MHz, fRF2 = 1900 MHz, fLO = 1697 MHz, each RF tone at 0 dBm 3.0 Resistor programmable Device disabled Min Typ 7.4 7.1 8.4 32 58 Max Unit dB dB dB dBm dBm
3.3 56 150
3.6
V mA A
Rev. 0 | Page 4 of 24
ADL5365 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Supply Voltage, VS RF Input Level LO Input Level IFOP, IFON Bias Voltage VGS0, VGS1, LOSW, PWDN Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering, 60 sec) Rating 5.5 V 20 dBm 13 dBm 6.0 V 5.5 V 1.2 W 25C/W 150C -40C to +85C -65C to +150C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 24
ADL5365 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCMI IFOP IFON PWDN COMM
VPMX RFIN RFCT COMM COMM
1 2 3 4 5
20 19 18 17 16
PIN 1 INDICATOR
ADL5365
TOP VIEW (Not to Scale)
15 LOI2 14 VPSW 13 VGS1 12 VGS0 11 LOI1
NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD. MUST BE SOLDERED TO GROUND.
VLO3 6 LGM3 7 VLO2 8 LOSW 9 NC 10
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4, 5, 16 6, 8 7 9 10 11, 15 12, 13 14 17 18, 19 20 Mnemonic VPMX RFIN RFCT COMM VLO3, VLO2 LGM3 LOSW NC LOI1, LOI2 VGS0, VGS1 VPSW PWDN IFON, IFOP VCMI EPAD (EP) Description Positive Supply Voltage. RF Input. Must be ac-coupled. RF Balun Center Tap (AC Ground). Device Common (DC Ground). Positive Supply Voltages for LO Amplifier. LO Amplifier Bias Control. LO Switch. LOI1 selected for 0 V, or LOI2 selected for 3 V. No Connect. LO Inputs. These pins must be ac-coupled. Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting. Positive Supply Voltage for LO Switch. Power-Down. Connect this pin to ground for normal operation or connect this pin to 3.0 V for disable mode. Differential IF Outputs. No Connect. This pin can be grounded. Exposed pad must be soldered to ground.
Rev. 0 | Page 6 of 24
08082-002
ADL5365 TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
VS = 5 V, IS = 95 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
110 100 TA = -40C 105
SUPPLY CURRENT (mA)
90
TA = +25C
TA = +85C 95
TA = +25C
INPUT IP2 (dBm)
100
80
70
TA = -40C 90
60 TA = +85C
85
50
08082-005
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 3. Supply Current vs. RF Frequency
10 10.0 9.5
Figure 6. Input IP2 vs. RF Frequency
TA = +85C
9
CONVERSION LOSS (dB)
9.0
SSB NOISE FIGURE (dB)
8.5 8.0 7.5 7.0 6.5 6.0 5.5
TA = +25C
8
TA = +85C
TA = -40C
7
TA = -40C
TA = +25C
6
RF FREQUENCY (MHz)
08082-014
RF FREQUENCY (MHz)
Figure 4. Power Conversion Loss vs. RF Frequency
40 38 TA = -40C 36
INPUT IP3 (dBm)
Figure 7. SSB Noise Figure vs. RF Frequency
34 TA = +85C 32 30 28
TA = +25C
RF FREQUENCY (MHz)
Figure 5. Input IP3 vs. RF Frequency
08082-011
26 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Rev. 0 | Page 7 of 24
08082-021
5 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
5.0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
08082-008
80 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
40 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
ADL5365
VS = 5 V, IS = 95 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
110 74 72 70
INPUT IP2 (dBm)
TA = +85C
TA = +25C
105
SUPPLY CURRENT (mA)
100 TA = +85C 95 TA = -40C TA = +25C
TA = -40C 68 66 64
90
85
62 60 -40
08082-016
08082-015
80 -40
-20
0
20
40
60
80
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 8. Supply Current vs. Temperature
10.0 9.5 9.0 TA = -40C TA = +25C TA = +85C
Figure 11. Input IP2 vs. Temperature
10.0 9.5 9.0
CONVERSION LOSS (dB)
8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 -40 -20 0 20 40 60 80
SSB NOISE FIGURE (dB)
VPOS = 5.25V
8.5
VPOS = 5.0V
8.0 7.5
VPOS = 4.75V
7.0 6.5 6.5 5.5
08082-022
TEMPERATURE (C)
08082-018
5.0 -40
-20
0
20
40
60
80
TEMPERATURE (C)
Figure 9. Power Conversion Loss vs. Temperature
40 38 36
Figure 12. SSB Noise Figure vs. Temperature
TA = +85C TA = -40C
TA = +25C
INPUT IP3 (dBm)
34 32 30 28 26 -40
-20
0
20
40
60
80
TEMPERATURE (C)
Figure 10. Input IP3 vs. Temperature
08082-017
Rev. 0 | Page 8 of 24
ADL5365
VS = 5 V, IS = 95 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
110 75
105
70
TA = +25C
SUPPLY CURRENT (mA)
TA = -40C 95 TA = +85C 90
TA = +25C
INPUT IP2 (dBm)
100
65
60
TA = -40C
TA = +85C
55 85
08082-003
80
130
180
230
280
330
380
430
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 13. Supply Current vs. IF Frequency
10.0 9.5 9.0
Figure 16. Input IP2 vs. IF Frequency
10.0 9.5 9.0 SSB NOISE FIGURE (dB) 8.5 8.0 7.5 7.0 6.5 6.0 5.5
08082-012
CONVERSION LOSS (dB)
8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 30 TA = +85C TA = +25C TA = -40C
80
130
180
230
280
330
380
430
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 14. Power Conversion Loss vs. IF Frequency
40 38 36 TA = +25C
Figure 17. SSB Noise Figure vs. IF Frequency
INPUT IP3 (dBm)
34 32 30 28 26 30
TA = +85C
TA = -40C
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
Figure 15. Input IP3 vs. IF Frequency
08082-009
Rev. 0 | Page 9 of 24
08082-020
5.0 30
08082-006
80 30
50 30
ADL5365
VS = 5 V, IS = 95 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
10.0 9.5 -40 -45 -50
CONVERSION LOSS (dB)
9.0 8.5 8.0 7.5 7.0 -80 6.5 6.0 -6 -85
08082-013 08082-027 08082-033
IF/2 SPURIOUS (dBc)
-55 -60 -65 -70 -75 TA = -40C TA = +25C TA = +85C
TA = +85C TA = +25C TA = -40C
-4
-2
0
2
4
6
8
10
-90 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 RF FREQUENCY (MHz)
2200
LO POWER (dBm)
Figure 18. Power Conversion Loss vs. LO Power
40 38 36 TA = -40C -40 -45 -50
Figure 21. IF/2 Spurious vs. RF Frequency
TA = +25C
IF/3 SPURIOUS (dBc)
TA = +85C
-55 -60 TA = +25C -65 -70 TA = -40C -75 -80 TA = +85C
INPUT IP3 (dBm)
34 32 30 28
-85
08082-010
26 -6
-4
-2
0
2
4
6
8
10
-90 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz)
LO POWER (dBm)
Figure 19. Input IP3 vs. LO Power
75 TA = -40C 70 TA = +25C TA = +85C 65
Figure 22. IF/3 Spurious vs. RF Frequency
INPUT IP2 (dBm)
60
55
-4
-2
0
2
4
6
8
10
LO POWER (dBm)
Figure 20. Input IP2 vs. LO Power
08082-007
50 -6
Rev. 0 | Page 10 of 24
ADL5365
VS = 5 V, IS = 95 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
100
36.5 36.0
3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 80 130 180 230 280 330 380 430 IF FREQUENCY (MHz)
08082-044 08082-030 08082-058
80
35.5 35.0
PERCENTAGE (%)
60
RESISTANCE ()
34.5 34.0 33.5 33.0 32.5 32.0
40
20
31.5
MEAN: 7.33 STANDARD DEVIATION:0.232
08082-059
31.0
7.8
0 6.8
7.0
7.2
7.4
7.6
30.5 30
CONVERSION LOSS (dB)
Figure 23. Conversion Loss Distribution
100
Figure 26. IF Output Impedance (R Parallel, C Equivalent)
0
80
5
RF RETURN LOSS (dB)
PERCENTAGE (%)
60
10
40
15
20 MEAN: 36.11 STANDARD DEVIATION: 0.146 34 36 INPUT IP3 (dBm) 38 40
08082-060
20
0 32
25 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
RF FREQUENCY (MHz)
Figure 24. Input IP3 Distribution
100 90 80
Figure 27. RF Port Return Loss, Fixed IF
0 5
LO RETURN LOSS (dB)
PERCENTAGE (%)
70 60 50 40 30 20
10 15 SELECTED
20 UNSELECTED 25 30
10 0 7.9
8.0 8.1 8.2
MEAN = 8.29 STANDARD DEVIATION = 0.30 8.3 8.4 8.5 8.6 8.7
08082-061
35 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 LO FREQUENCY (MHz)
NOISE FIGURE (dB)
Figure 25. SSB Noise Figure Distribution
Figure 28. LO Return Loss, Selected and Unselected
Rev. 0 | Page 11 of 24
CAPACITANCE (pF)
ADL5365
VS = 5 V, IS = 95 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
70 -20 -22 65
LO SWITCH ISOLATION (dB) LO-TO-RF LEAKAGE (dBm)
-24 -26 -28 -30 -32 -34 -36 -38
08082-034
60 TA = -40C 55
TA = -40C
50
TA = +25C TA = +85C
TA = +25C
45
TA = +85C
RF FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 29. LO Switch Isolation vs. RF Frequency
-40 -42 -44
RF-TO-IF ISOLATION (dBc)
0 -5
Figure 32. LO-to-RF Leakage vs. LO Frequency
TA = +85C
2LO LEAKAGE (dBm)
-46 -48 -50 -52 -54 -56 -58
TA = +25C
-10 -15 -20 -25 -30 -35 -40 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000
LO FREQUENCY (MHz) 2LO TO RF
TA = -40C
2LO TO IF
08082-032
RF FREQUENCY (MHz)
Figure 30. RF-to-IF Isolation vs. RF Frequency
0 -5
LO-TO-IF LEAKAGE (dBm)
-20 -25 -30
Figure 33. 2LO Leakage vs. LO Frequency
-10
3LO LEAKAGE (dBm)
-35 -40 -45 -50 -55 -60 -65
-15 -20 -25 -30 -35
TA = -40C TA = +25C TA = +85C
3LO TO RF
3LO TO IF
08082-028
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 31. LO-to-IF Leakage vs. LO Frequency
Figure 34. 3LO Leakage vs. LO Frequency
Rev. 0 | Page 12 of 24
08082-026
-40 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000
-70 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000
08082-025
-60 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
08082-029
40 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
-40 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000
ADL5365
VS = 5 V, IS = 95 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
10 9 8
CONVERSION LOSS (dB)
VGS = 0, VGS = 0, VGS = 1, VGS = 1,
0 1 0 1
15 14 GAIN 13
SSB NOISE FIGURE (dB)
25
20
SSB NOISE FIGURE (dB)
08082-043
7 6 5 4 3 2 1 NOISE FIGURE
12 11 10 9 8 7 6
15
10
5
-25
-20
-15
-10
-5
0
5
10
RF FREQUENCY (MHz)
BLOCKER POWER (dBm)
Figure 35. Power Conversion Loss and SSB Noise Figure vs. RF Frequency
40 38 36
INPUT IP3 (dBm)
Figure 38. SSB Noise Figure vs.10 MHz Offset Blocker Power
130
VGS = 0, VGS = 0, VGS = 1, VGS = 1,
0 1 0 1
120
SUPPLY CURRENT (mA)
110 100
34 32 30 28 26 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz)
90 80 70
08082-042
800
1000
1200
1400
1600
1800
BIAS RESISTOR VALUE ()
Figure 36. Input IP3 vs. RF Frequency
CONVERSION LOSS (dB) AND SSB NOISE FIGURE (dB)
Figure 39. Supply Current vs. Bias Resistor Value
10.5 10.0 9.5 9.0 8.5
NOISE FIGURE INPUT IP3
40 38 36 34 32 30 28 26
800 1000 1200 1400 1600 1800 BIAS RESISTOR VALUE ()
INPUT IP3 (dBm)
8.0 7.5 7.0 600
CONVERSION LOSS
Figure 37. Power Conversion Loss, SSB Noise Figure, and Input IP3 vs. IF Bias Resistor Value
Rev. 0 | Page 13 of 24
08082-041
08082-040
60 600
08082-019
5 0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
0 -30
ADL5365
3.3 V PERFORMANCE
VS = 3.3 V, IS = 56 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, R9 = 226 , VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
60 59 70 58 75
SUPPLY CURRENT (mA)
57 56 55 54 53 52 TA = -40C
TA = +25C
65
INPUT IP2 (dBm)
TA = +85C 60 55 50 45 TA = -40C TA = +25C
TA = +85C
51
08082-039 08082-036 08082-038
50 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz)
40 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz)
Figure 40. Supply Current vs. RF Frequency at 3.3 V
10.0 9.5 9.0 10.0 9.5 9.0
Figure 43. Input IP2 vs. RF Frequency at 3.3 V
TA = +85C TA = +25C
CONVERSION LOSS (dB)
8.0 TA = +85C 7.5 7.0 6.5 6.0 5.5
08082-035
NOISE FIGURE (dB)
8.5
8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz) TA = -40C
TA = +25C
TA = -40C
5.0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz)
Figure 41. Power Conversion Loss vs. RF Frequency at 3.3 V
35 33 31 TA = -40C
Figure 44. SSB Noise Figure vs. RF Frequency at 3.3 V
INPUT IP3 (dBm)
TA = +85C 29 27
25 23 TA = +25C
RF FREQUENCY (MHz)
Figure 42. Input IP3 vs. RF Frequency at 3.3 V
08082-037
21 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Rev. 0 | Page 14 of 24
ADL5365
UPCONVERSION
TA = 25C, fIF = 153 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
9.0 9.0
8.5
8.5
CONVERSION LOSS (dB)
CONVERSION LOSS (dB)
8.0
TA = +85C
TA = +25C
8.0
7.5 TA = -40C 7.0
7.5 TA = +85C 7.0 TA = -40C TA = +25C
6.5
08082-048
6.5
6.0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz)
6.0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz)
Figure 45. Power Conversion Loss vs. RF Frequency, VS = 5 V, Upconversion
35 33 31 TA = -40C
Figure 47. Power Conversion Loss vs. RF Frequency at 3.3 V, Upconversion
35 33
31
INPUT IP3 (dBm)
29 27
TA = +85C
INPUT IP3 (dBm)
TA = +25C
29
TA = -40C
27 TA = +85C 25 TA = +25C
25
23
08082-046
23
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 46. Input IP3 vs. RF Frequency, VS = 5 V, Upconversion
Figure 48. Input IP3 vs. RF Frequency at 3.3 V, Upconversion
Rev. 0 | Page 15 of 24
08082-045
21 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
21 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
08082-047
ADL5365
SPURIOUS PERFORMANCE
(N x fRF) - (M x fLO) spur measurements were made using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = -100 dBm.
5 V Performance
VS = 5 V, IS = 95 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
0 0 1 -42.2 2 -75.8 3 <-100 4 5 6 7 N 8 9 10 11 12 13 14 15 1 -10.9 0.0 -76.5 -83.0 <-100 2 -28.3 -49.3 -64.6 <-100 <-100 3 -44.5 -31.2 -78.4 -73.5 <-100 <-100 4 -49.8 -78.5 -90.9 <-100 <-100 <-100 5 6 7 M 8 9 10 11 12 13 14 15
-94.7 -89.8 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100
3.3 V Performance
VS = 3.3 V, IS = 56 mA, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, R9 = 226 , VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
M 0 0 1 -41.9 2 -72.3 3 -94.6 4 5 6 7 N 8 9 10 11 12 13 14 15 1 -16.9 0.0 -80.3 -71.6 <-100 2 -35.1 -49.1 -62.7 <-100 <-100 3 -61.4 -30.4 -68.5 -61.2 <-100 <-100 4 -52.6 -71.9 -92.7 <-100 <-100 <-100 5 6 7 8 9 10 11 12 13 14 15
<-100 -75.1 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100
Rev. 0 | Page 16 of 24
ADL5365 CIRCUIT DESCRIPTION
The ADL5365 consists of two primary components: the radio frequency (RF) subsystem and the local oscillator (LO) subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. In addition, the need for external components is minimized, optimizing cost and size. The RF subsystem consists of an integrated, low loss RF balun, passive MOSFET mixer, and a sum termination network. The LO subsystem consists of an SPDT-terminated FET switch and a three-stage limiting LO amplifier. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. A block diagram of the device is shown in Figure 49.
VCMI
20
The resulting balanced RF signal is applied to a passive mixer that commutates the RF input with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. As the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (M x N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the IF output. This termination is accomplished by the addition of a sum network between the IF output and the mixer. The IP3 performance can be optimized by adjusting the supply current with an external resistor. Figure 37 and Figure 39 illustrate how various bias resistors affect the performance with a 5 V supply. Additionally, dc current can be saved by increasing the resistor. It is permissible to reduce the dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the part. (Note that no performance enhancement is obtained by reducing the value of these resistors and excessive dc power dissipation may result.)
IFOP
19
IFON
18
PWDN
17
COMM
16
ADL5365
VPMX 1
15
LOI2
RFIN 2
14
VPSW
LO SUBSYSTEM
The LO amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation performance. The resulting amplifier provides extremely high performance centered on an operating frequency of 1700 MHz. The best operation is achieved with either high-side LO injection for RF signals in the 1200 MHz to 1700 MHz range or low-side injection for RF signals in the 1700 MHz to 2500 MHz range. Operation outside these ranges is permissible, and conversion gain is extremely wideband, easily spanning 1200 MHz to 2500 MHz, but intermodulation is optimal over the aforementioned ranges. The ADL5365 has two LO inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. The two inputs are applied to a high isolation SPDT switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the LO sources. This multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted LO input that may result in undesired IF responses. The single-ended LO input is converted to a fixed amplitude differential signal using a multistage, limiting LO amplifier. This results in consistent performance over a range of LO input power. Optimum performance is achieved from -6 dBm to +10 dBm, but the circuit continues to function at considerably lower levels of LO input power.
RFCT 3 BIAS GENERATOR COMM 4
13
VGS1
12
VGS0
COMM 5
6 7 8 9 10
11
LOI1
NC = NO CONNECT
Figure 49. Simplified Schematic
RF SUBSYSTEM
The single-ended, 50 RF input is internally transformed to a balanced signal using a low loss (<1 dB) unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. The RF balun can easily support an RF input frequency range of 1200 MHz to 2500 MHz.
Rev. 0 | Page 17 of 24
08082-051
VLO3
LGM3
VLO2
LOSW
NC
ADL5365
The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. The bandwidth of the intermodulation performance is somewhat influenced by the current in the LO amplifier chain. For dc current sensitive applications, it is permissible to reduce the current in the LO amplifier by raising the value of the external bias control resistor. For dc current critical applications, the LO chain can operate with a supply voltage as low as 3.3 V, resulting in substantial dc power savings. In addition, when operating with supply voltages below 3.6 V, the ADL5365 has a power-down mode that permits the dc current to drop to <200 A. All of the logic inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1.4 V. All logic inputs are high impedance up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection circuitry permits operation up to 5.5 V, although a small bias current is drawn.
Rev. 0 | Page 18 of 24
ADL5365 APPLICATIONS INFORMATION
BASIC CONNECTIONS
The ADL5365 mixer is designed to up- or downconvert between radio frequencies (RF) from 1200 MHz to 2500 MHz and intermediate frequencies (IF) from dc to 450 MHz. Figure 50 depicts the basic connections of the mixer. It is recommended to ac-couple RF and LO input ports to prevent non-zero dc voltages from damaging the RF balun or LO input circuit. The RFIN capacitor value of 3 pF is recommended to provide the optimized RF input return loss for the desired frequency band. For upconversion, the IF input, Pin 18 (IFON) and Pin 19 (IFOP), must be driven differentially or by using a 1:1 ratio transformer for single-ended operation. A 3 pF capacitor is recommended for the RF output, Pin 2 (RFIN).
BIAS RESISTOR SELECTION
An external resistor, RBIAS LO, is used to adjust the bias current of the integrated amplifiers at the LO terminals. It is necessary to have a sufficient amount of current to bias the internal LO amplifier to optimize dc current vs. optimum IIP3 performance. Figure 37 and Figure 39 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and IP3 performance.
MIXER VGS CONTROL DAC
The ADL5365 features two logic control pins, Pin 12 (VGS0) and Pin 13 (VGS1), that allow programmability for internal gate-to-source voltages for optimizing mixer performance over desired frequency bands. The evaluation board defaults both VGS0 and VGS1 to ground. Power conversion loss, NF, and IIP3 can be optimized, as shown in Figure 35 and Figure 36.
IF PORT
The real part of the output impedance is approximately 50 , as seen in Figure 26, which matches many commonly used SAW filters without the need for a transformer. This results in a voltage conversion loss that is approximately the same as the power conversion loss, as shown in Table 3.
IF1_OUT T1 R1 0
C25 560pF +5V 4.7F +5V 10pF
20 19
C24 560pF
18 17
10k
16
ADL5365
1 15
22pF LO2_IN
3pF RF-IN
2 14
+5V 10pF
3
13
0.01F
10pF
BIAS GENERATOR
4 12
22pF
5 6 7 8 9 10 11
LO1_IN
RBIAS LO +5V 10pF 10pF
10k
08082-052
Figure 50. Typical Application Circuit
Rev. 0 | Page 19 of 24
ADL5365 EVALUATION BOARD
An evaluation board is available for the family of double balanced mixers. The standard evaluation board schematic is shown in Figure 51. The evaluation board is fabricated using Rogers(R) RO3003 material. Table 7 describes the various configuration options of the evaluation board. Evaluation board layout is shown in Figure 52 to Figure 55.
IF1_OUT T1 R1 0
C25 560pF
C24 560pF PWR_UP R21 10k
R14 0
L3 0
IFON
IFOP
COMM
PWDN
VCMI
C12 22pF LO2_IN LOI2 VPSW VPOS
VPOS C2 10F RF-IN C1 3pF C5 0.01F C4 10pF C21 10pF
VPMX RFIN RFCT COMM COMM
C20 10pF C22 1nF VGS1 VGS0
R22 10k R23 15k
ADL5365
VGS1 VGS0 LOI1
LGM3
VLO3
VLO2
LOSW
NC
LO1_IN C10 22pF
VPOS C6 10pF R9 1.1k C8 10pF VPOS R4 10k
LOSEL
Figure 51. Evaluation Board Schematic
Rev. 0 | Page 20 of 24
08082-053
ADL5365
Table 7. Evaluation Board Configuration
Components C2, C6, C8, C20, C21 C1, C4, C5 T1, R1, C24, C25 Description Power Supply Decoupling. Nominal supply decoupling consists of a 10 F capacitor to ground in parallel with a 10 pF capacitor to ground positioned as close to the device as possible. RF Input Interface. The input channels are ac-coupled through C1. C4 and C5 provide bypassing for the center taps of the RF input baluns. IF Output Interface. T1 is a 1:1 impedance transformer used to provide a single-ended IF output interface. Remove R1 for balanced output operation. C24 and C25 are used to block the dc bias at the IF ports. LO Interface. C10 and C12 provide ac coupling for the LO1_IN and LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input for both mixer cores. R4 provides a pull-down to ensure that LO1_IN is enabled when the LOSEL test point is logic low. LO2_IN is enabled when LOSEL is pulled to logic high. PWDN Interface. R21 pulls the PWDN logic low and enables the device. The PWR_UP test point allows the PWDN interface to be exercised using the an external logic generator. Grounding the PWDN pin for nominal operation is allowed. Using the PWDN pin when supply voltages exceed 3.3 V is not allowed. Bias Control. R22 and R23 form a voltage divider to provide 3 V for logic control, bypassed to ground through C22. VGS0 and VGS1 jumpers provide programmability at the VGS0 and VGS1 pins. It is recommended to pull these two pins to ground for nominal operation. R9 sets the bias point for the internal LO buffers. R14 sets the bias point for the internal IF amplifier. Default Conditions C2 = 10 F (Size 0603), C6, C8, C20, C21 = 10 pF (Size 0402) C1 = 3 pF (Size 0402), C4 = 10 pF (Size 0402), C5 = 0.01 F (Size 0402) T1 = TC1-1-13M+ (Mini-Circuits), R1 = 0 (Size 0402), C24, C25 = 560 pF (Size 0402) C10, C12 = 22 pF (Size 0402), R4 = 10 k (Size 0402)
C10, C12, R4
R21
R21 = 10 k (Size 0402)
C22, L3, R9, R14, R22, R23, VGS0, VGS1
C22 = 1 nF (Size 0402), L3 = 0 (Size 0603), R9 = 1.1 k (Size 0402), R14 = 0 (Size 0402), R22 = 10 k (Size 0402), R23 = 15 k (Size 0402), VGS0 = VGS1 = 3-pin shunt
Rev. 0 | Page 21 of 24
ADL5365
Figure 52. Evaluation Board Top Layer
08082-054
Figure 54. Evaluation Board Power Plane, Internal Layer 2
08082-055
Figure 53. Evaluation Board Ground Plane, Internal Layer 1
Figure 55. Evaluation Board Bottom Layer
Rev. 0 | Page 22 of 24
08082-057
08082-056
ADL5365 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
15 16 20 1
PIN 1 INDICATOR
3.20 3.10 SQ 3.00
5
PIN 1 INDICATOR
4.75 BSC SQ
0.65 BSC
EXPOSED PAD
(BOTTOM VIEW)
TOP VIEW 0.70 0.65 0.60
0.75 0.60 0.50
11
10
6
2.60 BSC FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.90 0.85 0.80 SEATING PLANE
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VHHC
Figure 56. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-20-5) Dimensions shown in millimeters
ORDERING GUIDE
Model ADL5365ACPZ-R7 1 ADL5365-EVALZ1
1
042209-B
0.35 0.28 0.23
0.05 MAX 0.01 NOM COPLANARITY 0.05 0.20 REF
Temperature Range -40C to +85C
Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel Evaluation Board
Package Option CP-20-5
Ordering Quantity 1,500 1
Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
ADL5365 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08082-0-10/09(0)
Rev. 0 | Page 24 of 24

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